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Created with Raphaël 2.2.019Jun1411987227May2616Print when sending as well.packetdebugpacketdebugA few uncommitted lines for finding acks with wrong index.Made some changes to the simulator to debug controller implementation.Added non-functional code for driver unload.mastermasterIntermidate version, some acking works.Merge branch 'master' of gitlab.control.lth.se:anders_blomdell/extctrl2014Correct sequence wrap around for simulator, add intermediate VxWorks code.Correct sequence wrap around for simulator, add intermediate VxWorks code.Merge branch 'master' of gitlab.control.lth.se:anders_blomdell/extctrl2014Make ethernet frames 60 bytes for those drivers that actually checksSmall test.Starting to implement receiving.Merge branch 'master' of gitlab.control.lth.se:anders_blomdell/extctrl2014Add toolsRemoved some references to old version of extctrlMerge branch 'master' of gitlab.control.lth.se:anders_blomdell/extctrl2014Before implementing transmit retriesBefore implementing transmit retriesSanity check packets before trying to decodeCleaning up mc directoryAdded missing .lc file.Python protocol simulator addedCommiting hijack drivers for mc (ABB IRC5 master controller)